The present invention relates generally to design methods and circuit examples of radiation hardening and more particularly to design methods and circuit examples that minimize, eliminate and/or utilize the effects of radiation dose rate induced photo-currents in electronic circuit functions.
Radiation can generate hole-electron pairs in the junction of a transistor, which results in a photo-current through the junction. The magnitude of the photo-current depends upon the radiation dose rate level, and the collection volume (e.g., transistor junction size) and may be independent of the gate-controlled current. The photo-current can be analogized to a radiation-controlled current source that persists even when the junction voltage approaches zero volts (0V). Radiation dose rate is measured as the equivalent radiation absorbed dose (Rad) in silicon (Si) per second and is expressed as Rad(Si)/s. In a radiation dose rate environment, the total current through a transistor is the sum of its gate-controlled current and its radiation dose rate induced photo-current. Photo-currents can shift and/or upset the function of an analog or digital circuit. An analog circuit is typically more susceptible than a digital circuit because its transistors are operated in their linear region and its circuit impedance is relatively high. A digital circuit is less susceptible than an analog circuit because its transistors are either off or saturated and its circuit impedance is relatively low. Even so, photo-currents can reduce the output drive strength (fan out) and slow down the timing of digital circuits.
Radiation hardening refers to design methods for reducing electronic circuit susceptibility to radiation and/or inhibiting circuit function. Special design methods and examples are presented herein for making analog and digital circuit functions either independent (i.e. immune) or dependent of radiation dose rate induced photo-currents.
In magnetoresistive random access memory (MRAM), data is stored by using an electric current to create a magnetic field for switching a magnetic direction of a ferromagnetic layer of a multilayer memory element (also known as a bit). An MRAM is described as a type of nonvolatile (NV) memory because a logical state of a memory element will persist even when power is removed from the memory device. Although there are other types of nonvolatile memory chips, MRAM allows rapid read and write sequences. And unlike dynamic random access memory (DRAM), MRAM does not require a constant flow of current to retain its data—thus consuming less power.
MRAM has historically been arranged in a two-dimensional (2D) array of MRAM bits with write line trace currents associated with each row and column of the array. A typical MRAM bit is structured as a multilayer element having two magnetic (ferromagnetic) layers separated by a spacer layer. A logical state of the MRAM bit may be determined by the relative orientation of the magnetization directions of the magnetic layers. Writing the logical state of the MRAM bit involves setting the relative orientations—this is typically done by applying an external magnetic field to the bit.
An MRAM typically uses controlled write current pulses to switch a magnetic bit between its low and high magnetoresistive states. When using a two-dimensional (2D) bit selection scheme, each of orthogonal X and Y trace currents must each be below the magnetic bit switching threshold, while the combined X and Y trace currents at their intersection (the selected bit location) must be above the magnetic bit switching threshold.
Thus, there are stringent requirements on the uniformity of MRAM bit switching thresholds across an MRAM array and on pulse current pulse magnitudes to ensure that half-selected bits do not write (switch logical state) while ensuring that fully-selected bits do write.
A typical MRAM requirement for military and space applications allows no bad writes below the radiation dose rate upset (DRU) level and only one bad write to a known address between the DRU and radiation dose rate survivability (DRS) levels. Since standard address inputs and latches are not reliable above the DRU level, the write operation must be inhibited above the DRU level.
FIG. 1(a) depicts an example simple analog current reference and switched current driver schematic. A reference current and voltage is established by series-connecting a resistor 102 and a diode-connected (gate coupled to drain) n-channel reference transistor 104 between the power rail (VDD) 108 and the ground rail (VSS) 110. The gate-drain of n-channel reference transistor 104 is connected to the gate of a second n-channel transistor 112 to configure the second n-channel transistor 112 as a current mirror. The voltage level of the gates of the two n-channel transistors 104, 112 is the reference voltage on circuit node 106. A p-channel transistor 114 is connected as a current switch between the drain of the n-channel current mirror transistor 112 and the power rail 108. A write select input 118 is connected to the gate of the p-channel current switch transistor 114 and serves as a switching input. The trace connecting the current mirror transistor 112 and the p-channel current switch transistor 114 is the write line trace 116.
When the write select 118 is high (inactive), the p-channel current switch transistor 114 is off and no current flows through the write line trace 116. When the write select 118 is low (active), the p-channel current switch transistor 114 is on and the current mirror transistor 112 mirrors the reference current in the resistor 102 and the n-channel reference transistor 104. The ration of the current in the write line trace 116 to the reference current is a function of the ration of mirror to reference transistor sizes—i.e., a function of the ratio of the size of the n-channel current mirror transistor 112 to the n-channel reference transistor 104.
FIG. 1(b) depicts transistor gate-currents and radiation photo-currents of the circuit of FIG. 1(a). The reference current is the sum of the n-channel reference transistor 104 gate-current 150 and radiation photo-current 152. As this current sum increases, the voltage across the resistor 102 increases and the reference voltage developed across the n-channel reference transistor 104 decreases. This in turn causes a shift in the current mirrored by the n-channel current mirror transistor 112.
With the write select input 118 high (inactive), the p-channel current switch transistor 114 is off and the write line trace 116 current becomes the smaller of the p-channel current switch transistor 114 radiation photo-current 160 and the sum of the n-channel current mirror transistor 112 gate current 154 and radiation photo-current 156. In this case, increasing radiation levels can lead to a false write even if the write select input is high (inactive).
With the write select input 118 low (active), the p-channel current switch transistor 114 is on and the write line trace 116 current becomes the smaller of the sum of the p-channel current switch transistor 114 gate current 158 and radiation photo-current 160 and the sum of the n-channel current mirror transistor 112 gate current 154 and radiation photo-current 156. In this case, increasing radiation levels lead to higher reference and write line trace 116 current magnitudes, which can in turn cause a false write to half-selected bits.
Even below the radiation dose rate upset (DRU) level, the radiation photo-currents can shift both the reference and write line trace 116 current magnitudes and upset the drive states of circuits of FIG. 1(a).